Usually, the switching elements of switching regulators are made of n-channel MOS (metal oxide semiconductor) transistors (referred to as NMOS transistors hereinafter).
For this type of NMOS transistor, the driving signal can be provided as either a high level or low level signal to the gate of the NMOS transistor so that the NMOS transistor is turned on/off and acts as a switching element.
In consideration of the advantage that a large current can flow to the gate of the NMOS transistor, a circuit using a bipolar transistor is often used as the driving circuit for providing the driving signal.
FIG. 8 is a circuit diagram illustrating an example of a conventional driving circuit.
In FIG. 8, 1 represents a control circuit; V.sub.cc represents a power source voltage; q.sub.1, q.sub.2 represent npn transistors used as output transistors; D represents a clamping circuit made of a number of diodes; and NT represents an NMOS transistor used as a switching element. The driving circuit comprises control circuit 1, clamping circuit D, and transistors q.sub.1 and q.sub.2.
The base of transistor q, is connected to output terminal 1a of control circuit 1; the collector is connected to power source voltage V.sub.cc ; and the emitter is connected to the collector of transistor q.sub.2.
The base of transistor q.sub.2 is connected to output terminal 1b of control circuit 1, and its emitter is connected to ground.
The middle point of the connection between the emitter of transistor q.sub.1 and the collector of transistor q.sub.2 becomes output terminal T.sub.out of the circuit in FIG. 8, and it is connected to the gate of NMOS transistor NT.
A clamping circuit D made of a number of diodes connected in series is connected in the forward direction from the base of transistor q.sub.1 and ground. The clamping circuit D is arranged to ensure high-speed operation of the driving circuit as it clamps the high-level output to prevent the high-level output at the output terminal T.sub.out from shooting above a prescribed potential.
In this configuration, when high-level output appears at output terminal T.sub.out, current i.sub.1 is sent from output terminal 1a of control circuit 1 to the base and clamping circuit D of transistor q.sub.1 ; when a low level is output from output terminal T.sub.out, current i.sub.2 is fed from output terminal 1b to the base of transistor q.sub.2.
As shown in FIG. 9, currents i.sub.1 and i.sub.2 output from control circuit 1 have an opposite phase relationship with respect to each other, and they are fed to transistors q.sub.1, clamping circuit D and the base of transistor q.sub.2.
As a result, transistors q.sub.1 and q.sub.2 are turned on/off in a complementary fashion with respect to each other. As shown in FIG. 9, rectangular-shaped output V.sub.out is obtained at output terminal T.sub.out.
This output V.sub.out is fed to the gate of NMOS transistor NT, so that NMOS transistor NT is turned on/off.
However, in the aforementioned conventional circuit, as seen from point A on the output side as shown in FIG. 8, there is a high dc impedance at the gate of NMOS transistor NT. Consequently, emitter current i.sub.1E of transistor q.sub.1 and collector current i.sub.2C of transistor q.sub.2 can flow only in the transition state when the gate of the NMOS transistor is switched from the off state to the on state or from the on state to the off state, while they do not flow in the other steady state.
In the aforementioned conventional circuit, both in the transition state and in the steady state, current i.sub.1 or i.sub.2 is always fed from control circuit 1 to the base and clamping circuit D of transistor q.sub.1 and the base of transistor q.sub.2. Consequently, the power consumption is high. This is a disadvantage.
That is, in the conventional circuit, even in the steady state, wasteful current still flows. In addition, when the operational speed is high, the feed currents i.sub.1 and i.sub.2 have to be large. Consequently, the high-speed switching operation and the low power consumption are contradictory to each other.
It is an object of this invention to provide a type of driving circuit which provides both a low power consumption and a high operational speed.